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Rev 0; 8/08
Current Monitor and Accumulator with Integrated Sense Resistor
General Description
The DS2741 current monitor/accumulator is a complete current-sensing, measuring, and accumulation device tailored for cost-sensitive, battery-powered applications in a small 3mm x 3mm TDFN package. As a result, the DS2741 is a key component in battery-charge control and remaining capacity-estimation applications. Through its I2C interface, the DS2741 gives the host system access to current measurement and accumulation registers. The 7-bit slave address is factory programmable, allowing up to 128 devices to be individually addressed by the host system.
Features
Complete, Low-Cost, Integrated Current-Sensing and Accumulation Solution with Serial Digital Output On-Board 38m Sense Resistor Current Measurement: Signed 10-Bit Bidirectional Measurement 2.5A Dynamic Range 1% Error at +25C 2% Error Over Temperature Current Accumulation: 0.247mAhr LSB 8.1Ahrs Full-Scale Range Industry-Standard I2C Interface with FactoryProgrammable Slave Address 2.5V to 4.5V Single-Supply Operation Low-Power Consumption: Active Current: 60A (typ) Sleep Current: 1A (typ) -20C to +70C Operating Range 14-Pin TDFN (3mm x 3mm x 0.8mm)
DS2741
Applications
Cell Phones PDAs Battery Monitor/Rechargers
Ordering Information
PART DS2741N+ DS2741N+T TEMP RANGE -20C to +70C -20C to +70C PIN-PACKAGE 14 TDFN-EP* 14 TDFN-EP*
+Denotes a lead-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad.
Typical Operating Circuit
TOP VIEW
Pin Configuration
RS- RS- RS- RS- SLP GND DNC
CHARGER/ LOAD
14 RS+
DS2741
13
12
11
10
9
8
RSDC-DC CONVERTER 1.8V Li + BATTERY
VCC
DS2741
EP* 2 3 4 5 6 7
SLP 0.1F GND SDA SCL
2.2k
2.2k MICROPROCESSOR
1
RS+ RS+ RS+ RS+ SDA SCL VCC
+
TDFN
*EXPOSED PAD
________________________________________________________________ Maxim Integrated Products
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Current Monitor and Accumulator with Integrated Sense Resistor DS2741
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to GND ...............-0.5V to +6.0V Voltage Range on SDA, SCL, RS+, RS-, SLP Relative to GND.....-0.5V to (VCC + 0.5V), not to exceed +6.0V Continuous Internal Sense Resistor Current ......................2.7A Pulsed Internal Sense Resistor Current ..................................10A for <100s/s, <1000 pulses Operating Temperature Range ...........................-20C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -20C to +70C.)
PARAMETER Supply Voltage Input Logic-High: SCL, SDA Input Logic-Low: SCL, SDA Input Logic-High: SLP Input Logic-Low: SLP Power-Up Ramp Time from 0V to VCCMIN SYMBOL VCC VIH VIL VIH VIL tRAMP 0.7 x VCC 0.3 x VCC 25 (Note 1) CONDITIONS MIN 2.5 1.5 0.4 TYP MAX 4.5 UNITS V V V V V ms
DC ELECTRICAL CHARACTERISTICS
(2.5V VCC 4.5V, TA = -20C to +70C.)
PARAMETER Active Current Sleep-Mode Current Output Logic-Low: SDA Internal Current-Sense Resistor Value Current Resolution Current Full-Scale Magnitude Current-Sense Accuracy at +25C Current-Sense Accuracy from 0C to +70C Current Sampling Rate Accumulator Resolution Internal Time-Base Accuracy Current-Sense Offset SYMBOL IACTIVE I SLEEP VOL RSNS ILSB IFS ATL ATL tCSR qCA t ERR1 t ERR2 (Note 4) (Note 4) Measured with RS+ and RS- shorted -10 (Note 2) I SENSE at 1.5A I SENSE at 1.5A (Note 3) 2.54 CONDITIONS SLP = SCL = SDA = VCC SLP = 0V I OL = 4mA (Note 1) +25C 0.4 38 2.64 2.7 1 2 200 0.247 1 3 6.5 +10 2 4 45 MIN TYP 60 1 MAX 90 2 UNITS A A V m mA A % % s mAh % mA
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Current Monitor and Accumulator with Integrated Sense Resistor
TEMPERATURE SENSOR CHARACTERISTICS
(VCC = +2.5V to +4.5V, TA = -20C to +70C, unless otherwise noted.)
PARAMETER Temperature Error SYMBOL CONDITIONS MIN TYP MAX 5 UNITS C
DS2741
AC ELECTRICAL CHARACTERISTICS: I2C INTERFACE
(2.5V VCC 4.5V, TA = -20C to +70C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 4.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB (Note 6) (Note 6) (Note 6) (Note 5) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF
Note 1: All voltages are referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 2: Compensation of the internal sense resistor value for initial tolerance and temperature coefficient of -20C to +70C can reduce the maximum reportable magnitude to 2.5A. Note 3: Current sampling ceases for 2.5ms every 144ms to allow the ADC to measure temperature. Note 4: Typical value for tERR1 is specified at 3.6V and +25C, max value is specified for 0C to +50C. Max value for tERR2 is specified for -20C to +70C. Note 5: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with standard-mode I2C timing. Note 6: CB--Total capacitance of one bus line in pF; timing referenced to 0.1 x VCC and 0.9 x VCC.
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Current Monitor and Accumulator with Integrated Sense Resistor DS2741
Typical Operating Characteristics
(VCC = +2.5V to +4.5V, TA = -20C to +70C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SLP = SDA = SCL = VCC TA = +25C
DS2741 toc01
SLEEP-MODE CURRENT vs. SUPPLY VOLTAGE
DS2741 toc02
SUPPLY CURRENT vs. TEMPERATURE
SLP = SDA = SCL = VCC = +3.5V 60 SUPPLY CURRENT (A) 50 40 30 20 10
DS2741 toc03
70 60 SUPPLY CURRENT (A) 50 40 30 20 10 0 2.5 3.0 3.5 4.0
2.0 SDA = SCL = VCC SLP = GND TA = +25C
70
SLEEP-MODE CURRENT (A)
1.5
1.0
0.5
0 4.5 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
0 -20 -10 0 10 20 30 40 50 60 70 TEMPERATURE (C)
SUPPLY CURRENT vs. SCL FREQUENCY
DS2741 toc04
DISTRIBUTION OF CURRENT-SENSE OFFSET
DS2741 toc05
INITIAL CURRENT-SENSE ACCURACY DISTRIBUTION
ISENSE AT 1.5A 247 SAMPLES
DS2741 toc06
70 60 SUPPLY CURRENT (A) 50 40 30 20 10 0 0 50 SLP = SDA = SCL = VCC = +3.5V TA = +25C
90 80 POPULATION OF PARTS 70 60 50 40 30 20
247 SAMPLES
60 50 POPULATION OF PARTS 40 30 20 10
10 0 100 150 200 250 300 350 400 SCL FREQUENCY (kHz) -10 -7 -4 -1 2 5 8 CURRENT-SENSE OFFSET (mA) 0 -2.0 -1.4 -0.8 -0.2 0.4 1.0 1.6 CURRENT-SENSE ACCURACY (%)
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Current Monitor and Accumulator with Integrated Sense Resistor
Pin Description
PIN 1-4 5 6 7 8 9 10 NAME RS+ SDA SCL VCC DNC GND SLP FUNCTION Sense Resistor High Side. Connection to high side of internal 38m must be connected together. sense resistor. All RS+ pins
DS2741
Serial Data Input/Output. SDA is the input/output pin for the I2C serial interface. The SDA pin is an open-drain output and requires an external pullup resistor. Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. Supply Voltage. Power-supply input. Do Not Connect Ground Sleep Input (Active Low). When taken low, the DS2741 is placed in a low-power sleep state where all internal circuitry including the I2C bus is disabled. Toggling the SLP pin low and then back high resets the device and the I2C bus logic. Sense Resistor Low Side. Connection to low side of internal 38m must be connected together. Exposed Pad. Can be left floating. sense resistor. All RS- pins
11-14 --
RSEP
Block Diagram
VCC SLP
SDA SCL
I2C INTERFACE
VOLTAGE REFERENCE
POWER CONTOL
CURRENT REGISTER CURRENT ACCUMULATOR REGISTER TEMPERATURE REGISTER GND
10-BIT PLUS SIGN A/D CONVERTER
DS2741
38m
RS+
RS-
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Current Monitor and Accumulator with Integrated Sense Resistor DS2741
Detailed Description
The DS2741 is a small, low-cost, current-sensing and accumulation IC that is intended for current-monitoring applications. The differential voltage measured across the on-chip 38m sense resistor is digitized by an internal ADC that provides an accurately scaled digital signed 10-bit value that represents bidirectional current up to 2.5A. The measured current result is reported in an internal SRAM register that can be read using the I 2 C interface. After each current measurement, the signed result value is added to an accumulator in order to maintain a signed accumulated current value with a 0.247mAhr LSB and a full-scale range of 8.1Ahrs. The device can be placed into a low-power sleep mode when current measurements are not needed. to be the filtered voltage drop across the sense resistor. A positive VRS value indicates current is flowing into the battery (charging), while a negative VRS value indicates current is flowing out of the battery (discharging). VRS is measured with a signed resolution of 10 bits. The current register is updated in two's-complement format every 22.7ms with an average of eight readings. Current measurements outside the register range are reported at the range limit. Figure 1 shows the format of the current register. The DS2741 maintains the current register in units of amps, with a resolution of 2.64mA and full-scale range of no less than 2.5A. The DS2741 automatically compensates for internal sense resistor process variations and temperature effects when reporting current.
Power Modes
The DS2741 has two power modes: active and sleep. While in active mode, the DS2741 continually measures and accumulates current and provides data to the host system through its I2C interface. In sleep mode, the DS2741 ceases these activities. The DS2741 enters sleep mode whenever an active-low signal is applied to the SLP pin and remains in sleep as long as the SLP pin is held low. Active mode resumes when the SLP pin is returned to a logic-high level. The SLP pin resets the Current and Temperature registers, but not the Current Accumulator register.
Current Accumulator
The current accumulator facilitates remaining capacity estimation by tracking the net current flow into and out of the battery. Current flow into the battery increments the current accumulator, while current flow out of the battery decrements it. The DS2741 maintains the current accumulator 0.247mAhrs resolution and full-scale value of 8.1Ahrs range. Data is maintained in the current accumulator in two's-complement format. Figure 2 shows the format of the current accumulator. The current accumulator is a read/write register that can be altered by the host system as needed. The Current Accumulator register is not reset when the DS2741 is in sleep mode.
Current Measurement
In active mode, the DS2741 continually measures the current flow into and out of the battery by measuring the voltage drop across the internally integrated 38m current-sense resistor. The DS2741 considers the voltage difference between pins RS+ and RS- (VRS = VRS+ - VRS-)
MSB--ADDRESS 16h S MSb 29 28 27 26 25 24 23 LSb
Temperature Measurement
The on-board temperature sensor measures temperatures from +127C to -128C. The LSb of register 14h has a 1C bit weight. See Figure 3 for the temperature register's two's-complement format.
LSB--ADDRESS 17h 22 MSb 21 20 X X X X X LSb
Figure 1. Current Register Format
MSB--ADDRESS 10h S MSb 214 213 212 211 210 29 28 LSb 27 MSb 26 LSB--ADDRESS 11h 25 24 23 22 21 20 LSb
Figure 2. Current Accumulator Register Format
ADDRESS 14h S MSb 26 25 24 23 22 21 20 LSb
Figure 3. Temperature Register Format
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Current Monitor and Accumulator with Integrated Sense Resistor
Registers
The DS2741 has 2-byte registers for current measurement and accumulation. When the MSB of a 2-byte register is read, both the MSB and LSB are latched and held for the duration of the read data command to prevent updates during the read and ensure synchronization between the two register bytes. For consistent results, always read the MSB and the LSB of a 2-byte register during the same read data command sequence.
DS2741
Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low, while SCL remains high, generates a START condition. See Figure 4 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high, while SCL remains high, generates a STOP condition. See Figure 4 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 4 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold-time requirements (see Figure 4). Data is shifted into the device during the rising edge of the SCL.
Table 1. Register Map
ADDRESS (HEX) 00h to 0Fh DESCRIPTION Reserved READ/WRITE -- R/W -- R -- R --
10h and 11h Current Accumulator Register 12h and 13h Reserved 14h 15h 18h to FFh Temperature Register Reserved Reserved
16h and 17h Current Register
I2C Bus Interface
I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions.
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 4. I2C Timing Diagram
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Current Monitor and Accumulator with Integrated Sense Resistor
Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 4) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse, and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes (see Figure 4). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so that the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave addressing byte sent immediately following a START condition. The slave address byte (Figure 5) contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS2741's default factory programmed 7-bit slave address is 0110100b (binary) or 68h (hex). By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the DS2741 assumes the master is communicating with another
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DS2741
7-BIT SLAVE ADDRESS 0 MOST SIGNIFICANT BIT 1 1 0 1 0 0 R/W DETERMINES READ OR WRITE
Figure 5. DS2741 Slave Address Byte
I2C device and ignores the communications until the next start condition is sent. This value can be changed at the factory to match the user's need. Contact the factory for more details on custom I2C device addresses for the DS2741. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
I2C Communication
See Figure 6 for examples of I2C communication. Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applica-
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Current Monitor and Accumulator with Integrated Sense Resistor DS2741 DS2741
COMMUNICATIONS KEY S P SR START STOP REPEATED START A N ACK NACK WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA 8-BIT ADDRESS OR DATA NOTES 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.
XXXXXXXX
WRITE TWO BYTES WITH A SINGLE TRANSACTION TO SLAVE ADRESS 68h S 01101000 A MEMORY ADDRESS A DATA A DATA A P
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER FROM SLAVE ADDRESS 68h S 01101000 A MEMORY ADDRESS A SR 0 1 1 0 1 0 0 1 A DATA N P
READ TWO BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER FROM SLAVE ADDRESS 68h S 01101000 A MEMORY ADDRESS A SR 0 1 1 0 1 0 0 1 A DATA A DATA N P
Figure 6. I2C Communications Examples
ble, and generates a STOP condition. See Figure 6 for a read example using the repeated START condition to specify the starting memory location. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it NACKs to indicate the end of the transfer and generates a STOP condition. This can be done with or without modifying the address counter's location before the read cycle. The DS2741's address counter does not wrap on page boundaries during read operations, but the counter rolls from its uppermost memory address FFh to 00h if the last memory location is read during the read transaction.
Applications Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power supply is decoupled with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS2741 that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC electrical characteristics are within specification.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 14 TDFN-EP PACKAGE CODE T1433+2 DOCUMENT NO. 21-0137
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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